angr.engines.light

class angr.engines.light.ArithmeticExpression

Bases: object

Add = 0
Sub = 1
Or = 2
And = 4
RShift = 8
LShift = 16
Mul = 32
Xor = 64
CONST_TYPES = (<class 'int'>, <class 'angr.ailment.expression.Const'>)
__init__(op, operands)
op
operands
static try_unpack_const(expr)
class angr.engines.light.RegisterOffset

Bases: object

__init__(bits, reg, offset)
reg
offset
property bits
property symbolic
class angr.engines.light.SimEngineLight

Bases: SimEngine, Generic

A full-featured engine base class, suitable for static analysis

block: BlockType
state: StateType
stmt_idx: int
ins_addr: int
tmps: dict[int, DataType_co]
__init__(project, logger=None)
Parameters:

project (Project)

abstractmethod process(state, *, block=None, **kwargs)
Return type:

TypeVar(ResultType)

Parameters:
lift(state)
Return type:

TypeVar(BlockType, bound= BlockProtocol)

Parameters:

state (StateType)

static sp_offset(bits, offset)
Return type:

BV

Parameters:
static extract_offset_to_sp(spoffset_expr)

Extract the offset to the original stack pointer.

Parameters:

spoffset_expr (Base) – The claripy AST to parse.

Return type:

int | None

Returns:

The offset to the original stack pointer, or None if spoffset_expr is not a supported type of SpOffset expression.

class angr.engines.light.SimEngineLightAIL

Bases: SimEngineLight[StateType, DataType_co, Block, ResultType], Generic

A mixin for doing static analysis on AIL

__init__(*args, **kwargs)
process(state, *, block=None, whitelist=None, **kwargs)
Return type:

TypeVar(ResultType)

Parameters:
  • state (StateType)

  • block (ailment.Block | None)

  • whitelist (set[int] | None)

class angr.engines.light.SimEngineLightVEX

Bases: SimEngineLight[StateType, DataType_co, Block, ResultType], Generic

A mixin for doing static analysis on VEX

tyenv: IRTypeEnv
static unop_handler(f)
Return type:

Callable[[TypeVar(T), Unop], TypeVar(DataType_co)]

Parameters:

f (Callable[[T, pyvex.expr.Unop], DataType_co])

static binop_handler(f)
Return type:

Callable[[TypeVar(T), Binop], TypeVar(DataType_co)]

Parameters:

f (Callable[[T, pyvex.expr.Binop], DataType_co])

static binopv_handler(f)
Return type:

Callable[[TypeVar(T), int, int, Binop], TypeVar(DataType_co)]

Parameters:

f (Callable[[T, int, int, pyvex.expr.Binop], DataType_co])

static triop_handler(f)
Return type:

Callable[[TypeVar(T), Triop], TypeVar(DataType_co)]

Parameters:

f (Callable[[T, pyvex.expr.Triop], DataType_co])

static qop_handler(f)
Return type:

Callable[[TypeVar(T), Qop], TypeVar(DataType_co)]

Parameters:

f (Callable[[T, pyvex.expr.Qop], DataType_co])

static ccall_handler(f)
Return type:

Callable[[TypeVar(T), CCall], TypeVar(DataType_co)]

Parameters:

f (Callable[[T, pyvex.expr.CCall], DataType_co])

static dirty_handler(f)
Return type:

Callable[[TypeVar(T), Dirty], TypeVar(StmtDataType)]

Parameters:

f (Callable[[T, pyvex.stmt.Dirty], StmtDataType])

__init__(*args, **kwargs)
process(state, *, block=None, whitelist=None, **kwargs)
Return type:

TypeVar(ResultType)

Parameters:
class angr.engines.light.SimEngineNoexprAIL

Bases: SimEngineLightAIL[StateType, DataType_co | None, StmtDataType, ResultType], Generic

A base class of SimEngineLightAIL that has default handlers for expressions if they just need to return None, so you don’t have to implement every single expression handler as return None.

class angr.engines.light.SimEngineNostmtAIL

Bases: SimEngineLightAIL[StateType, DataType_co, StmtDataType | None, ResultType], Generic

A base class of SimEngineLightAIL that has default handlers for statements if they just need to return None, so you don’t have to implement every single statement handler as return None.

class angr.engines.light.SimEngineNostmtVEX

Bases: SimEngineLightVEX[StateType, DataType_co, ResultType, None], Generic

A base class of SimEngineLightVEX that has default handlers for statements if they just need to return None, so you don’t have to implement every single statement handler as return None.

class angr.engines.light.SpOffset

Bases: RegisterOffset

__init__(bits, offset, is_base=False)
is_base

Submodules