[docs]classNameResolutionMixin(MemoryMixin):""" This mixin allows you to provide register names as load addresses, and will automatically translate this to an offset and size. """def_resolve_location_name(self,name,is_write=False):# Delayed load so SimMemory does not rely on SimEnginesfrom...engines.vex.claripy.ccallimport_get_flagsifself.category=="reg":ifself.state.arch.namein("X86","AMD64"):ifnameinstn_map:return(((stn_map[name]+self.load("ftop"))&7)<<3)+self.state.arch.registers["fpu_regs"][0],8elifnameintag_map:return((tag_map[name]+self.load("ftop"))&7)+self.state.arch.registers["fpu_tags"][0],1elifnamein("flags","eflags","rflags"):# we tweak the state to convert the vex condition registers into the flags registerifnotis_write:# this work doesn't need to be done if we're just gonna overwrite itself.store("cc_dep1",_get_flags(self.state))# constraints cannot be added by thisself.store("cc_op",0)# OP_COPYreturnself.state.arch.registers["cc_dep1"]ifis_arm_arch(self.state.arch):ifname=="flags":ifnotis_write:self.store("cc_dep1",_get_flags(self.state))self.store("cc_op",0)returnself.state.arch.registers["cc_dep1"]ifname=="sp"and"sp"notinself.state.arch.registers:sp_reg_name=self.state.arch.register_names[self.state.arch.sp_offset]returnself.state.arch.registers[sp_reg_name]ifname=="lr"and"lr"notinself.state.arch.registers:lr_reg_name=self.state.arch.register_names[self.state.arch.lr_offset]returnself.state.arch.registers[lr_reg_name]returnself.state.arch.registers[name]elifname[0]=="*":returnself.state.registers.load(name[1:]),Noneelse:raiseSimMemoryError("Trying to address memory with a register name.")